S. Deepa ¹

Affiliations
1 Indian Institute of Management, Kozhikode, Kunnamangalam - 673570, Kerala, IN

Abstract

Objective: To analyze the existence of computer-related health problems among white-collar employees; and to suggest a blueprint for prevention. Methods/Statistical Analysis: A study was conducted across segments among white-collar employees from South India with a participant volume of 259. The chi-square test in SPSS version 22 was used for analyzing the results. Findings: The existence of visual problems in the participant set was 65% (168/259), and musculoskeletal problems were conveyed by 67% (173/259) whilst 32% (84/259) experienced stressful signs. The study established that there was a steady upsurge in visual complaints as the total hours working on computers added day by day. Similar link was discovered for musculoskeletal complications. Improvements/Applications: A lot of research on the topic has been done already. The blueprint that should be communicated to the employees to tackle the computer-related health concerns makes it exclusive. The evidence can be used by employers to cultivate a practice and very essentially, will navigate them in building a well-informed workforce. It will also facilitate them modify the workplace to augment employer branding.

Keywords

Action Plan, Health Problems, Standardized Nordic Questionnaire, White-Collar Employees.

Full Text

   

M. Aalelai Vendhan ¹, S. Deepa ¹

Affiliations
1 Department of Electronics and Communication Engineering, Panimalar Engineering College, Chennai – 600123, Tamil Nadu, IN

Abstract

Objectives: To reduce the leakage power dissipation and minimize the propagation delay, a Fin FET based 8-bit adder architecture is constructed. The performance metrics of these structures are calculated over a range of temperatures and are compared with the MOSFET based 8-bit adder architecture. Various logic styles are utilized for constructing the adder. Method/Analysis: A Ripple carry adder structure is employed. The existing adder architecture is constructed using 90nm MOSFET technology. The proposed adder architecture is constructed using 32nm FINFET technology. The various logic styles employed are Complementary Metal-Oxide Semiconductor logic (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate logic (TG) and Gate Diffusion Input logic (GDI). Cadence Virtuoso is used for designing purpose and simulation is performed using Spectre. Findings: Key performance metrics like static power, dynamic power, leakage power, delay and power delay product are calculated. The dynamic power of MOSFET architecture ranges from 7.42μW to 882.6μW. The dynamic power of FINFET architecture ranges from 0.407nW to 156.2nW. The static power (inputs at high logic level) of MOSFET architecture ranges from 0.001μW to 945.76μW. The static power (inputs at high logic level) of Fin FET architecture ranges from 0.725pW to 170.4nW. The static power (inputs at low logic level) of MOSFET architecture ranges from 0.94nW to 1.68mW. The static power (inputs at low logic level) of Fin FET architecture ranges from 0.127pW to 305.3nW. The leakage power (inputs at high logic level) of MOSFET architecture ranges from 1.27nW to 134.7μW. The leakage power (inputs at high logic level) of Fin FET architecture ranges from 0.36pW to 24.77nW. The leakage power (inputs at low logic level) of MOSFET architecture ranges from 0.54nW to 139.9μW. The leakage power (inputs at low logic level) of Fin FET architecture ranges from 0.15nW to 227.6nW. The delay of MOSFET architecture ranges from 0.344μs to 0.46μs. The delay of Fin FET architecture ranges from 0.19μs to 0.28μs. The power delay product of MOSFET architecture ranges from 2.66 to 405.99. The power delay product of Fin FET architecture ranges from 0.83 to 29.67. Novelty/Improvements: The FINFET adder architecture proved to be effective in reducing the propagation delay and leakage power dissipation. This may find usage in high performance devices like microchips and supercomputers.

Full Text